Tecnologia1 mintechpowerup.com10/08/2026
Intel Nova Lake-S iGPU with 12 Xe3P Cores to Feature 40 W PL2 and 20 MB of L2 Cache
According to the reliable Intel leaker Jaykihn, Intel's upcoming "Nova Lake-S," featuring 12 Xe3P cores, currently has a Power Limit 2 (PL2) setting of about 40 W. This builds on…

According to the reliable Intel leaker Jaykihn, Intel's upcoming "Nova Lake-S," featuring 12 Xe3P cores, currently has a Power Limit 2 (PL2) setting of about 40 W. This builds on the previous rumor that this integrated graphics solution will arrive with two VCCGT phases for up to 65 W of power. This SKU includes four P-Cores, eight E-Cores, and four LPE-Cores, along with 12 Xe3P GPU cores. This 4+8+4 CPU core and 12 GPU core configuration is one of the few processors where integrated graphics require two VCCGT phases. In regular SKUs, VCCGT is a single-phase power rail for the integrated graphics inside the processor.
However, we now know that the PL2 setting will only use 40 W, as the 65 W threshold is set for extreme scenarios like PL3, and the graphics processor's PL4 is capped at that 65 W figure. The Xe3P features more microarchitectural changes compared to the Xe3 found in "Panther Lake." If readers recall, a 12 Xe3-core iGPU found in "Panther Lake" has 16 MB of L2 cache, while the Xe3P iGPU dedicated to "Nova Lake" will have a 20 MB L2 cache configuration, a 25% increase. More L2 cache means that some workloads will naturally benefit, but we still don't know preliminary performance. The Xe3P microarchitecture is expected to carry more changes, especially since it has a larger L2 cache.
However, we now know that the PL2 setting will only use 40 W, as the 65 W threshold is set for extreme scenarios like PL3, and the graphics processor's PL4 is capped at that 65 W figure. The Xe3P features more microarchitectural changes compared to the Xe3 found in "Panther Lake." If readers recall, a 12 Xe3-core iGPU found in "Panther Lake" has 16 MB of L2 cache, while the Xe3P iGPU dedicated to "Nova Lake" will have a 20 MB L2 cache configuration, a 25% increase. More L2 cache means that some workloads will naturally benefit, but we still don't know preliminary performance. The Xe3P microarchitecture is expected to carry more changes, especially since it has a larger L2 cache.
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